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May 22, 2012 –
Towards a formal, automated chip design monitoring system, by Michel Tabusse in EETimes
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May 14, 2012 –
The Process of Process Tracking - Satin Technologies Attempts to Corral a Recalcitrant Beast, by Bryon Moyer in EEJournal
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May 14, 2012 –
Satin to introduce automated design monitoring at DAC 2012, by Clive Maxfield in EETimes
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April 4, 2011 –
How to achieve quality assurance for your electronic designs ?, by Clive Maxfield in Programmable Logic Design Line
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February 23, 2011 –
Dashboards : A history of improving quality, by Michel Tabusse in dac.com
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December 16, 2010 –
Collaboration Penalty is Steep for Engineers (John Blyler's discussion with Cliosoft, Numetrics and Satin Tech.)
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December 6, 2010 –
Analog Design Quality Closure : What's Missing from Current Flows ?, by Stephane Bonniol in EETimes
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March 17, 2010 –
EDA is not enough !, by Michel Tabusse in EDA DesignLine
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December 9, 2009 –
Panelists look at IP quality versus design productivity, by Anne-Françoise Pelé, EETimes
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December 4, 2009 –
Design Quality Closure : Enabling less design iteration at every handover in a design process, by Michel Tabusse in GSA Forum
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November 16, 2009 –
Use formal, online communication to deliver design quality closure, by Stephane Bonniol in EDA DesignLine
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July 22, 2009 –
The business of IP : it ain’t a bake sale, by Peggy Aycinena, EDA Design Line
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July 16, 2009 –
EDA firms to improve design for mask manufacturing, by Anne-Françoise Pelé, EETimes Europe
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June 30, 2009 –
IP Inexact : A look at Life in the IP World, by Bryon Moyer, IC Design and Verification Journal
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June 23, 2009 –
How will the IEEE’s emerging QIP standard contribute to IP design quality closure ?, by Michel Tabusse (View point in Chip Design Magazine)
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May 5, 2008 –
SCD Source : New exhibitors bring fresh ideas to DAC (by R. Goering)
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Apr 2007 –
EETimes - EDA startup boosts design-for-reuse
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