VIP Lane
Overview
VIP Lane® is an enterprise software solution for fact-based design quality monitoring and closure. Working within customers' design flows, VIP Lane turns customers' design practices (for IP blocks, SoCs, embedded systems) into a robust and reliable set of quality criteria and metrics. These customer-based parameters are used to create automated, sharable dashboards and quality compliance reports.
By providing an alternative to manually filled, time-consuming checklists and documents, VIP Lane® shortens time-to-market by delivering effective flow integration and on-the-fly quality monitoring at zero overhead to design teams.
VIP Lane® addresses the challenges of design quality closure from 4 complementary perspectives:
a. Project managers' perspective, or "How can I monitor design quality in a factual and cost effective way, despite all design dynamics and a multi-location organization?"
b. Designers' perspective, or "CanI check how my work complies with corporate quality rules and metrics without additional engineering effort?"
c. Design methodology perspective, or "How can we easily deploy, monitor and maintain best design practices throughout our design teams?"
d. Quality assurance perspective, or "How can we support all design reviews and process audits by generating the most appropriate documents, so that conformance to quality standards becomes an easier challenge?"
VIP Lane® answers these questions by implementing a 3-step strategy:
| 1. Import your Design Quality Checks and metrics by using one of the available libraries or by creating your own library in a few hours | |
| 2. Configure and Automate Dashboards by editing software sensors that link the Quality Checks to your current design and verification flow | |
| 3. Monitor Design Quality Closure by deploying the dashboards and issuing quality conformance on the fly |
Once deployed, VIP Lane® is a web server application that is integrated with and complements the electronic design automation (EDA) and product lifecycle management tools that typically constitute semiconductor design flows.