Technology
Design quality monitoring and reporting can make the difference between meeting delivery schedules and not meeting them, between one-pass silicon and expensive respins, between meeting a market window and missing it entirely. Rather than adding a new EDA technology into the design flow, it is possible to integrate automated design quality checking directly into a flow to turn existing design practices into a robust set of quality criteria and to do quality monitoring on the fly.
System-on-chip (SoC) designers, embedded systems designers and mask shop engineers have something in common: The quality of what they deliver can only be as good as what they get from the teams before them. For example, SoC designers expect developers of intellectual property (IP) to deliver blocks that are ready for smooth integration, and mask shop engineers expect backend designers to deliver graphic design system (GDS) data that are design-for-mask-manufacturing (DFMM)-aware.
SoC designers and mask shop engineers see their common challenge ("expecting the most out of their respective predecessors") from different perspectives: while significant effort is put into defining quality standards for IP, little formalism is available to those interested in breaking down the wall between design houses and mask shops. However, regardless of where they stand in the design chain, engineering and product managers now spend between 20 and 40 percent of their time tracking the design quality metrics that they consider critical. This time could be dramatically reduced with a more formal understanding of what constitutes design quality, and with an easier way for designers to check quality run after run.
More specifically, at DFMM level, stopping any mask during mask processing, which requires a waiver from the customer, will add a delay of between 12 and 24 hours to its delivery schedule, depending on the stage during which the problem is detected. In the worst case, the mask will pass normal inspection, allowing a too-well-defined, repeated defect to kill the wafer, when this defect could have been anticipated. Since such quality issues are usually discovered very late in the entire process, up to the final circuit testing before packaging, they can often delay the entire project by a month or more.
A methodology for resolving these issues is through "design quality closure" (DQC), which can be defined as the condition of passing an acceptable subset of predefined quality checks for safe handover to the next engineering team. This, of course, requires a set of predefined quality checks (also known as methodology rules, guidelines or best practices) with which designers must comply, as well as a configurable design quality closure tool to monitor and report compliance. Closure happens when the designer is sufficiently confident that all critical parameters are met, so that his design work can be carried out to the next phase, without putting the chip objectives at risk (function, area, timing, power, manufacturability, testability, etc...)
Quality metrics exist to some extent, but have, until recently, been rules that must be tracked manually. The Quality of Electronic and Software Intellectual Property (QIP) metric standard, for instance, allows companies to evaluate IP from internal groups or third parties. However, since it is based on Excel spreadsheets, it adds another layer of labor to designers' loads. Design quality closure is more useful if applied automatically to all steps of a chip design process. DQC's characteristics are reuse of quality standards when available, openness to user specifics (design flow, know-how, etc.), and opportunity to formalize and deploy new quality rules over time.
Design, mask making and process engineering have always seen themselves as separate areas that seem to depend on sets of rules that isolate them from having to understand one another's technology. However, the ever-increasing number and complexity of these design rules is making the traditional isolated design paradigm unsupportable. Today, close interaction between the manufacturing, mask and design communities is a key to successful product development.
An optimized design quality closure tool
A key aspect of design quality closure is to incorporate quality checks throughout the entire design flow. A DQC tool allows a
designer to take advantage of an existing design flow, synthesize all the EDA artifacts into easy-to-read dashboards, and make
design decisions on the basis of factual design data. By automatically generating quality reports, such a tool can save weeks
of time. The DQC tool tracks and captures all parameters and objects affecting design quality from multiple sources throughout
the IP or SoC design and integration lifecycle, and offers "checklist-driven" design assistance to help users monitor
specifications, coding, integration, frontend/backend implementation, verification, and all other relevant tasks.
A design quality closure tool turns many flow artifacts into automated dashboards
Ideally, a DQC tool implements a three-phase approach. First, it helps companies set up their design methodologies by importing hundreds of pre-written design quality checks easily. Second, it automates the quality checks. Finally, it supports the methodology deployment to all involved design teams with automatically filled dashboards and quality closure reports.
For maximum flexibility and utility, such a DQC tool would allow the designer to import design quality checks by using one of the available libraries or by creating a unique library in a few hours. It would then configure and automate dashboards by editing software sensors that link the quality checks to the current design and verification flow, and permit design quality closure monitoring by deploying the dashboards and issuing quality reports on-the-fly.
A design quality closure tool allows integration of libraries from multiple sources
The functioning of such a tool is most optimal when it provides non-intrusive assistance to the designer. This capability is exemplified by dashboards that complete themselves automatically, on the basis of the latest information found in the customer flow, and that reflect the set of quality items that designers need to monitor. The dashboards must address the most critical areas of design quality and design reuse: specifications, architecture, front-end design, back-end design, verification, IP packaging, software development and overall project management. In addition, they should be generated on-the-fly from the customer flow outputs. They should be available in different forms (single IP, multicore design, etc...), and always up to date, by construction. This allows fact-based quality closure monitoring by project managers, and complements the other mechanisms that the managers have for tracking resources and schedules, making a major contribution to timely and accurate quality closure.
Applying design quality closure to design-for-reuse
It is generally accepted that reusing semiconductor IP blocks in a core-based design strategy is the most suitable response to the stringent constraints involved in SoC design. The principal challenges for design-for-reuse can be summarized as follows:
- The quality of an IP block is defined by its ability to be integrated safely into an SoC, which involves careful management of various engineering practices throughout the block life cycle.
- For large semiconductor companies, implementing a quality-based strategy to reuse IP blocks is one of the strategic targets to reduce the costs, risks and design timelines of complex integrated circuits.
- For IP vendors, it is absolutely vital to produce the highest quality IP possible, and to be able to document that quality for prospective customers.
Designers and integrators of reusable blocks cannot meet their objectives merely by using the most up-to-date EDA software along with design guidelines too loose or too general to really make a difference. It is absolutely crucial that design guidelines (whether stipulated by manufacturers or public literature) be applied on a daily basis by all the teams involved in block development. Each engineer, whatever his or her involvement in the project, must be able to identify and assess the quality requirements relating to his or her particular activity.
Among the most essential issues that must be considered to guarantee the success of a design-for-reuse strategy are:
- Enforcing design-for-reuse practices
Once defined at a corporate level, stable design-for-reuse practices should be enforced through the design teams, without incurring unwanted engineering overhead.
- Managing design dynamics
Changing specifications and test cases are part of real-life designs, and should be dealt with efficiently. Instead of relying on hard copies or Excel spreadsheets that are time-consuming and error-prone, and that eventually become obsolete, design documents should be issued automatically from the design environment, with up-to-date information.
- Ensuring stable design-for-reuse criteria
Large semiconductor corporations usually find added productivity in homogenizing their design flows through the teams. However, even standardized design flows evolve constantly with added capabilities, new needs to inter-operate with customers and partners, etc. Benefits result from insulating design-for-reuse criteria monitoring from the multiple and changing EDA tools, file formats and databases.
Applying design quality closure to design for mask manufacturing
Such industry initiatives as the European CRYSTAL collaborative research and development program are intended to significantly improve DFMM by identifying and formalizing recommended design practices to make mask manufacturing a more efficient and less iterative process. The goal is to help improve design consistency, on-time delivery and the cost of photomask design by providing access to real data about 1) the manufacturing challenges at mask shops and 2) the design practices in the upstream design phases that would solve these challenges. Such initiatives would also align the development and availability of the real-time data points to the need for leading-edge design libraries in addition to the standard libraries.
Specific mask-level issues that need to be addressed in the manufacturing process include:
- Grid mismatch between design and fractured data. This generally causes micro gaps and shape border offsets.
- Sub-geometries created during optical proximity correction (OPC) application, which will generate mask inspection issues.
- Metal layer filling with "wild" cutting, which generates acute angles and sub-geometries.
- Multi-project wafers, with exceeded process tolerance window when several designs are assembled.
A design quality closure tool that uses real manufacturing data can highlight these issues before it is too late. For example, it can check possible grid mismatch by snapping between the design and desired fractured data and by analyzing the fracturing log report for on-grid geometries. It can also check the number of sub-geometries smaller than the minimum feature size after the OPC application step and the number or acute angles after the metal layer filling step.
This type of design test usually exists at a different level of data generation, but never compares results to the mask process requirements, the type of mask process which will be used being unknown by the designers. In addition, the set of rules that will be used for the final mask manufacturing are not introduced early enough in the design flow to be captured in the first design quality checks.
Summary ...
Added design productivity comes with streamlining the design flows and processes that semiconductor companies have in place. This in turn requires the documentation and implementation of robust handover procedures between engineering teams that follow each other sequentially. Two real life examples are a) the need for IP designers to measure their deliveries with respect to quality criteria that make a positive impact on SoC integration, and b) the need for SoC backend designers to prevent mask manufacturability issues by adopting DFMM-specific practices.
A formalized strategy for design quality closure, with associated monitoring tool and dedicated quality check libraries, is of major help for facilitating and strengthening handovers. It helps designers to deliver work in complete awareness of what the next team in the design process is expecting from them.
Such a strategy covers the needs of those design teams using standard quality checks and metrics (e.g., QIP for IP design practices) and supports the definition and deployment of proprietary practices when no standard is available (e.g., DFMM).
To all it brings added design quality, productivity and predictability, and this makes design quality closure a must-have capability in today's design environments.
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